Towards Smart System Architectures: A Fuzzy MCDM-Based Evaluation of Application Mapping Strategies
Abstract
Application mapping strategies in Network-on-Chip (NoC)-based Multiprocessor System-on-Chip (MPSoC) are critical for achieving efficient communication and reduced energy consumption. Therefore, choosing the optimal mapping strategy is of significant importance. However, due to the numerous evaluation criteria, trade-offs, conflict, and criteria importance, the assessment and selection of mapping strategies remain a complex challenge. Despite the importance of this issue, current literature reveals a significant research gap in comprehensive comparative evaluations of these strategies using systematic and quantitative methods. Previous researchers recommended multi-criteria decision-making (MCDM) to address the issue of identity best mapping strategy. Remarkably, the literature has reported a paucity of evaluations of the optimal mapping strategies. The present study aims to determine the most effective application mapping strategies in certain situations by using fuzzy MCDM methods. The design and methods of this study involve two phases. The first phase involves the evaluation decision matrix, which is derived through the intersection of the evaluation criteria and the mapping strategies list. The second phase includes the proposed MCDM methods, namely the Weight Fuzzy Judgment Method with Triangular Fuzzy (TrWFJM) for determining the weights for the criteria of mapping strategies and MultiAttributive Border Approximation Area Comparison (MABAC) to rank the mapping strategies based on the weight assigned. The findings of Tr-WFJM revealed that PIP Cost has the highest final weight (0.2326) and MPEG-4 Cost has the lowest weight (0.0887), respectively. In terms of the MABAC method, the Integer Linear Programming (ILP) is the most efficient mapping strategy. This study is exceptional because it provides academics and practitioners insight into reducing resources and energy consumption.
References
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S. Tosun, O. Ozturk, and M. Ozen, “An ILP formulation for application mapping onto networkon-chips,” in International conference on application of information and communication technologies, 2009, pp. 1–5.
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M. Obaidullah and G. N. Khan, “Application mapping to mesh NoCs using a tabu-search based swarm optimization,” Microprocessors and Microsystems, vol. 55, pp. 13–25, 2017.
Y. Li and P. Zhou, “Fast and accurate NoC latency estimation for application-specific traffics via machine learning,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 9, pp. 3569–3573, 2023.
M. Darbandi, A. R. Ramtin, and O. K. Sharafi, “Tasks mapping in the network on a chip using an improved optimization algorithm,” International Journal of Pervasive Computing and Communications, vol. 16, no. 2, pp. 165–182, 2020.
J. Choudhary, C. S. Sudarsan, and J. Soumya, “A performance-centric ML-based multiapplication mapping technique for regular Network-on-Chip,” Memories-Materials, Devices, Circuits and Systems, vol. 4, p. 100059, 2023.
A. A. J. Al-Hchaimi et al., “Prioritizing Network-On-Chip Routers for Countermeasure Techniques against Flooding Denial-of-Service Attacks: A Fuzzy Multi-Criteria Decision-Making Approach,” Computer Modeling in Engineering & Sciences , vol. 142, no. 3. 2025. doi: 10.32604/cmes.2025.061318.
A. A. J. Al-Hchaimi, A. H. M. Alaidi, Y. R. Muhsen, M. F. Alomari, N. Bin Sulaiman, and M. U. Romdhini, “Optimizing Energy and QoS in VANETs through Approximate Computation on Heterogeneous MPSoC,” in 4th International Conference on Emerging Smart Technologies and Applications (eSmarTA), 2024, pp. 1–6.
D. Grover, T. Sharma, S. Agarwal, S. S. Rout, M. Kumar, and S. Deb, “NoCiPUF: NoC-Based Intrinsic PUF for MPSoC Authentication,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2025.
T. Nagalaxmi, E. S. Rao, and P. Chandrasekhar, “Design and Performance Analysis of Low Latency Routing Algorithm based NoC for MPSoC,” International Journal of Communication Networks and Information Security, vol. 14, no. 1s, pp. 37–53, 2022.
R. Pop and S. Kumar, “A survey of techniques for mapping and scheduling applications to network on chip systems,” School of Engineering, Jonkoping University, Research Report, vol. 4, no. 4, 2004.
R. Dafali and J.-P. Diguet, “MPSoC architecture-aware automatic NoC topology design,” in Network and Parallel Computing: IFIP International Conference, NPC 2010, Zhengzhou, China, September 13-15, 2010. Proceedings, 2010, pp. 470–480.
P. Narayanasamy and S. Gopalakrishnan, “Novel fault tolerance topology using corvus seek algorithm for application specific NoC,” Integration, vol. 89, pp. 146–154, 2023.
Z. Li et al., “Hotspots reduction for GALS NoC using a low-latency multistage packet reordering approach,” Micromachines, vol. 14, no. 2, p. 444, 2023.
S. Ramesh, K. Manna, V. C. Gogineni, S. Chattopadhyay, and S. Mahapatra, “CongestionAware Vertical Link Placement and Application Mapping Onto Three-Dimensional NetworkOn-Chip Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., 2024.
J. Soumya and S. Chattopadhyay, “Application-specific network-on-chip synthesis with flexible router placement,” Journal of Systems Architecture., vol. 59, no. 7, pp. 361–371, 2013.
S. Tosun, “Cluster-based application mapping method for network-on-chip,” Advances in Engineering Software, vol. 42, no. 10, pp. 868–874, 2011.
J. Hu and R. Marculescu, “Energy-aware mapping for tile-based NoC architectures under performance constraints,” in Proceedings of the 2003 Asia and South Pacific Design Automation Conference, vol. 2003-Janua, pp. 233–239, 2003, doi: 10.1109/ASPDAC.2003.1195022.
J. Hu and R. Marculescu, “Energy-and performance-aware mapping for regular NoC architectures,” IEEE Transactions on computer-aided design of integrated circuits and systems, vol. 24, no. 4, pp. 551–562, 2005.
M. Reshadi, A. Khademzadeh, and A. Reza, “Elixir: a new bandwidth-constrained mapping for networks-on-chip,” IEICE Electronics Express, vol. 7, no. 2, pp. 73–79, 2010.
F. Moein-darbari, A. Khademzadeh, and G. Gharooni-fard, “Evaluating the performance of a chaos genetic algorithm for solving the network on chip mapping problem,” in International Conference on Computational Science and Engineering, 2009, vol. 2, pp. 366–373.
M. Tavanpour, A. Khademzadeh, S. Pourkiani, and M. Yaghobi, “GBMAP: an evolutionary approach to mapping cores onto a mesh-based NoC architecture,” Journal of Communication and Computer, vol. 7, no. 3, pp. 1–7, 2010.
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Published
2025-08-24
How to Cite
MUHSEN, Yousif Raad et al.
Towards Smart System Architectures: A Fuzzy MCDM-Based Evaluation of Application Mapping Strategies.
Yugoslav Journal of Operations Research, [S.l.], aug. 2025.
ISSN 2334-6043.
Available at: <https://yujor.fon.bg.ac.rs/index.php/yujor/article/view/1364>. Date accessed: 26 sep. 2025.
doi: https://doi.org/10.2298/YJOR250515032R.
Issue
Section
Research Articles
This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.
